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Jeff McVeigh, the VP and GM of Intel’s super compute group, announced today via a blog post that Intel is canceling its upcoming Rialto Bridge series of data center Max GPUs and moving to a two-year cadence for data center GPU releases. Therefore the company’s next data center GPU offerings will come in the form of the Falcon Shores chiplet-based hybrid chips, but the blog notes these will be in production in 2025 — a year later than Intel’s previous projections of 2024.
The HPC-focused Falcon Shores XPUs are designed for supercomputing applications and merge both CPU and GPU technology into one mix-and-match chip package, but they will now first arrive as a GPU-only architecture in 2025. These were supposed to arrive as a CPU+GPU architecture in 2024, meaning Intel’s positioning against competing AMD and Nvidia products, both of which will launch this year, is severely impacted — Intel will now be multiple years late to a key architectural inflection point for the highest-end chips (more on that further below).
Additionally, Intel will cancel its upcoming Lancaster Sound GPU for its Flex Series of data center GPUs. These GPUs are designed for lower-intensity work, like media encoding. Instead of pushing forward with Lancaster Sound, Intel will focus on the next-gen Melville Sound products for the Flex series.
Intel says the new release cadence is based upon customer expectations for data center GPU products, and it does generally match the incremental launch rate we see from other GPU companies, like Nvidia. The moves come in the wake of Intel’s recent restructuring of its AXG graphics group to address the gaming and data center markets separately by placing it under two other business units. The restructuring was designed to increase focus on the end markets served by the GPU products, and these new developments represent a further narrowing of focus. In addition, Intel says that it will now improve its focus on its software ecosystem and provide continuous updates for the Max and Flex series GPUs that include more performance, features, and expanded operating system support.
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Intel’s Falcon Shores XPU is key to competing with Nvidia’s Grace Hopper Superchips and AMD Instinct MI300 Data Center APU. Nvidia’s Grace and AMD’s MI300 are both launching this year with both CPU and GPU cores on the same package with HBM memory. These designs represent a new type of architecture that confers massive advantages for HPC workloads, and that will be difficult to impossible to match with hardware based on existing designs.
Intel tells us that the delayed Falcon Shores will first come with only GPU cores in 2025, but hasn’t indicated when it will integrate CPU cores into the design. As such, Intel’s HPC-centric designs will lag behind its competitors for several years. Additionally, Intel will be forced to compete with AMD and Nvidia’s HPC-centric designs with its Xeon CPUs and Ponte Vecchio GPUs for several years, a significant disadvantage.
Falcon Shores represents the continuation of Intel’s heterogeneous architecture design arc with the end goal of delivering 5X the performance per watt, 5X the compute density in an x86 socket, and 5X the memory capacity and bandwidth of existing server chips. Intel’s roadmap of both CPUs and GPUs for High Performance Computing (HPC) converge with Falcon Shores, indicating these chips will serve both roles in the future.
This disaggregated chip design will eventually have separate tiles of x86 compute and GPU cores, but Intel can use those tiles to create any mixture of the two additives, like an all-CPU model, an all-GPU model, or a mixed ratio of the two. Intel notes that these tiles will be fabbed on an unspecified Angstrom-era process node, though Intel’s 20A seems to fit the bill for the tiles it could fab itself.
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Intel’s current-gen Ponte Vecchio GPUs were meant to be followed by Rialto Bridge, the planned next-gen data center GPU slated for 2023. That won’t happen now, so Intel will be forced to use Ponte Vecchio to compete with Nvidia’s Hopper H100, a key shortcoming at a time when LLMs like ChatGPT are coming to the fore and driving billions in Capex investments.
Rialto Bridge wouldn’t have helped Intel much in its competition against Nvidia’s incredibly powerful H100, though. Intel originally divulged that Rialto would feature up to 160 Xe cores, a substantial increase over the 128 cores present on Ponte Vecchio. In addition, the chip was said to come with unspecified architectural enhancements, similar to a “tick,’ that would confer up to a 30% performance improvement in applications over Ponte Vecchio. Intel listed Rialto Bridge’s peak power consumption at 800W, an increase over Ponte Vecchio’s 600W peak. Rialto Bridge was compatible with Ponte Vecchio packaging, so it was designed to be a drop-in upgrade.
|AMD vs. Intel Roadmap||2022||2023||2024|
|Intel P-Cores||Sapphire Rapids – Intel 7 – 56 Cores||Emerald Rapids – Intel 7||Granite Rapids – Intel 3|
|AMD P-Cores||Milan-X – 7nm | Genoa – 5nm – 96 Cores||?||?|
|Intel E-Cores||—||—||Sierra Forest – Intel 3|
|AMD E-Cores||—||Bergamo – 5nm – 128 Cores||?|
On the data center side of the house, Intel says that its Xeon products remain on track and, more critically, that its process node roadmap is on schedule as well.
However, Intel doesn’t plan to release of its Sierra Forest processors, a special hyperscale-optimized chip, until 2024. Meanwhile, AMD’s Bergamo will arrive this year, meaning that Intel will lag its competition in yet another crucial architectural advance for an extended period of time.
Likewise, Intel’s decision to slow its GPU release cadence isn’t ideal as it will have to leverage older products to compete with far more advanced architectures for HPC, like Nvidia’s Grace Superchips and AMD’s coming exascale APU, the Instinct MI300, that both launch in 2023.